View SA8028_150274.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
SA8028
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
Product data Supersedes data of 2002 Jan 09 File under Integrated Circuits -- IC17 2002 Feb 22
Philips Semiconductors
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
GENERAL DESCRIPTION
The SA8028 BICMOS device integrates programmable dividers, charge pumps and phase comparators to implement phase-locked loops. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies. The synthesizer operates at VCO input frequencies up to 2.5 GHz. The synthesizer has fully programmable RF, IF, and reference dividers. All divider ratios are supplied via a 3-wire serial programming bus. The RF divider is a fractional-N divider with programmable integer ratios from 33 to 509 and a fractional resolution of 22 programmable bits (23 bits internal). A 2nd order sigma-delta modulator is used to achieve fractional division. Separate power and ground pins are provided to the charge pumps and digital circuits. VDDCP must be equal to or greater than VDD. The ground pins should be externally connected to prevent large currents from flowing across the die and thus causing damage. The charge pump current (gain) is fully programmable, while ISET is set by an external resistance at the RSET pin (refer to section 1.5, RF and IF Charge Pumps). The phase/frequency detector charge pump outputs allow for implementing a passive loop filter.
APPLICATIONS * 500 to 2500 MHz wireless equipment * Cellular phones, all standards including:
CDMA 3G GSM TDMA GAIT : IS95-B,C WCDMA : WCDMA / UMTS : EDGE / GPRS : IS136 and EDGE : GSM and TDMA
* * * *
WLAN Wireless PDAs Satellite tuners and all other high frequency equipment Extreme fine frequency resolution applications
STROBE 20
LOCK
TEST
VDDPre
1 2 3 4 5 6 7 PHP
24
V DD
23
22
21
19 18 17 CLOCK REFin+ REFin- RSET VDDCP N/C
FEATURES * Extremely low phase noise: * * * * * * *
L(f) = -101 dBc/Hz at 5 kHz offset at 800 MHz Low power Programmable Normal & Integral charge pump outputs: Maximum output = 10.4 mA Digital fractional spurious compensation Hardware and software power-down IDDsleep < 0.1 A (typ) at VDD = 3.0 V Seperate supply for VDD and VDDCP Programmable loop filter bandwidth
GND GNDPre RFin+ RFin- GNDCP
TOP VIEW
16 15 14
8 PHI
9 GND CP
10 PHA
11 IFin
12 N/C
13
DATA
PON
SR02176
Figure 1. HBCC24 pin configuration.
ORDERING INFORMATION
TYPE NUMBER PACKAGE NAME SA8028W HBCC24 DESCRIPTION Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (CSP package) VERSION SOT564-1
2002 Feb 22
2
853-2277 27777
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
QUICK REFERENCE DATA
VDDCP = VDD = VDDpre= +3.0 V, Tamb = +25C; unless otherwise specified. SYMBOL VDD, VDDpre VDDCP IDDtotal IDDsleep fRFin fIFin fREFin fCOMPMAX Tamb PARAMETER Digital supply voltage Charge pump supply voltage Total supply current Total supply current in power-down mode VCO Input frequency range Input frequency range Crystal reference input frequency Maximum phase comparator frequency Operating ambient temperature RF phase comparator; max. limit is indicative CONDITIONS VDD = VDDpre VDDCP VDD, VDDpre RF and IF. on MIN. 2.7 2.7 - - 500 100 5 - -40 TYP. - - 7.6 0.1 - - - - - MAX. 3.6 3.6 - 1 2500 760 30 30 +85 UNIT V V mA A MHz MHz MHz MHz C
2002 Feb 22
3
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
VDD 24 18 CLOCK DATA 19 2-BIT SHIFT REGISTER 22-BIT SHIFT REGISTER PUMP CURRENT SETTING PUMP BIAS
VDDpre 1
VDDCP 14
STROBE
20
ADDRESS DECODER
CONTROL LATCH
15
RSET
LOAD SIGNALS SIGMA-DELTA 4 RFin+ RFin- 5 RF DIVIDER PHASE DETECTOR 7 PHP LATCH
8 LATCH REFin+ REFin- 17 16 REF DIVIDER 2 2 22
PHI
SA
LOCK DETECT
22
LOCK
LATCH IFin 11 IF DIVIDER
PHASE DETECTOR
10
PHA
TEST
23 2 GND 3 GNDPre 6, 9 GNDCP
21
PON
SR02379
Figure 2. HBCC24 Block Diagram
HBCC24 PIN DESCRIPTION
SYMBOL VDDpre GND GNDPre RFin+ RFin- GNDCP PHP PHI GNDCP PHA IFin N/C PIN 1 2 3 4 5 6 7 8 9 10 11 12 DESCRIPTION Prescaler supply voltage Ground; digital Prescaler ground; analog Input to RF divider (+) Input to RF divider (-) Charge pump ground; analog RF normal charge pump output RF integral charge pump output Charge pump ground; analog IF charge pump output Input to IF divider Not connected VDD 24 SYMBOL N/C VDDCP RSET REFin- REFin+ CLOCK DATA STROBE PON LOCK TEST PIN 13 14 15 16 17 18 19 20 21 22 23 DESCRIPTION Not connected Charge pump supply voltage; analog External resistor from this pin to ground sets the charge pump current Input to reference (-) Input to reference (+) Programming bus clock input Programming bus data input Programming bus enable input Power-down control input Lock detect output Test (should be either grounded or connected to VDD) Supply; digital
2002 Feb 22
4
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
LIMITING VALUES
In accordance with the Absolute Maximum Rating System SYMBOL VDD VDDCP VDDpre VDD Vn VGND Tstg Tamb Tj PARAMETER Digital supply voltage Charge pump supply voltage Analog supply voltage Difference in supply voltages VDDCP - VDDpre (VDDCP VDDpre, VDD) All input pins Difference in voltage between GNDpre, GNDCP and GND (these pins should be connected together) Storage temperature Operating ambient temperature Maximum junction temperature MIN. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -40 MAX. +3.6 +3.6 +3.6 +0.9 VDD + 0.3 +0.3 +125 +85 150 UNIT V V V V V V C C C
Handling
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL Rth j-a PARAMETER HBCC24: Thermal resistance from junction to ambient in still air VALUE 30 UNIT C/W
2002 Feb 22
5
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
CHARACTERISTICS
VDDCP = VDD = VDDpre= +3.0 V, Tamb = +25C; unless otherwise specified. SYMBOL Supply VDD, VDDpre VDDCP IDDTotal Digital supply voltage, prescaler supply voltage Charge pump supply voltage Synthesizer operational total supply current VDD = VDDpre VDDCP VDD, VDDpre fREF = 20 MHz (with RF on, IF on) (with RF on, IF off) IDDsleep fRFin VRFin Total supply current in power-down mode RF VCO input frequency range AC-coupled input signal level Rin (external) = Rs = 50 ; single-ended drive; g max. limit is indicative @ 500 to 2500 MHz fRFin = 2.4 GHz fRFin = 2.4 GHz Limited test coverage RF phase comparator logic levels 0 or VDD RF divider input 500 -15 112 - - 33 - 100 fIFin: 100 MHz to 500 MHz Rin (external) = RS = 50 ; max. limit is indicative fIFin: 500 MHz to 760 MHz Rin (external) = RS = 50 ; max. limit is indicative ZFin CFin NIF fREFin VREFin ZREFin CREFin RREF RSET VSET ICP IMATCH IZOUT ILPH VPH Input impedance Re (Z) Typical pin input capacitance IF division ratio Input frequency range from TCXO AC-coupled input signal level Input impedance Re (Z) Typical pin input capacitance Reference division ratio External resistor from pin to ground Regulated voltage at pin Charge pump current ratio to ISET1 Sink-to-source current matching Output current variation versus VPH2 Charge pump off leakage current Charge pump voltage compliance RSET = 7.5 k Current gain = IPH/ISET VPH = 1/2 VDDCP VPH in compliance range VPH = 1/2 VDDCP single-ended drive; max. limit is indicative fREF = 20 MHz fREF = 20 MHz SA = "000", IF loop fRFin = 500 MHz fRFin = 500 MHz -15 112 -10 200 - - 128 5 360 - - 4 6 - -15 -10 -10 -10 0.6 - - - 300 1 - - - - - - - 3.9 0.5 - - - 10 1 - 7.5 1.22 - - - - - 2500 0 632 - - 509 30 760 0 632 0 632 - - 16383 30 1300 - - 1023 15 - +15 +10 +10 +10 VDDCP-0.7 k V % % % nA V MHz mVPP k pF MHz MHz dBm mVpp dBm mVpp k pF MHz dBm mVpp pF 2.7 2.7 - - - - - 7.6 6.4 0.1 3.6 3.6 - - 1 V V mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ZRFin CRFin NRF FCOMPmax fIFin VIFin
Input impedance Re (Z) Typical pin input capacitance RF divider ratio ranges Maximum phase comparator frequency Input frequency range AC-coupled input signal level
IF divider input
Reference divider input
Charge pump current setting resistor input
Charge pump outputs; RSET = 7.5 k
2002 Feb 22
6
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
SYMBOL
PARAMETER Synthesizer's contribution to close-in phase noise of 900 MHz RF signal at 5 kHz offset. Synthesizer's contribution to close-in phase noise of 1800 MHz RF signal at 5 kHz offset. Synthesizer's contribution to close-in phase noise of 800 MHz RF signal at 5 kHz offset. Synthesizer's contribution to close-in phase noise of 2100 MHz RF signal at 5 kHz offset.
CONDITIONS fREF = 13 MHz, TCXO, fCOMP = 13 MHz indicative, not tested As above fREF = 19.44/19.68 MHz, TCXO, fCOMP = 19.44/19.68 MHz indicative, not tested As above
MIN. -
TYP. -99
MAX. -
UNIT dBc/Hz
Phase noise (condition RSET = 7.5 k, CP = 00, non speed-up mode)
L(f)
- -
-93 -101
- -
dBc/Hz dBc/Hz
-
-93
-
dBc/Hz
Interface logic input signal levels VIH VIL ILEAK HIGH level input voltage LOW level input voltage Input leakage current VDD = 3 V, VIH = 3 V, VIL = 0 V Isink = 2 mA Isource = -2 mA 0.7*VDD -0.3 -0.5 - - - VDD+0.3 0.3*VDD +0.5 V V A
Lock detect output signal (in push/pull mode) and Data output signal (in readout test mode) VOL VOH NOTES: 1.
SET bias current for charge pumps. R SET 2. The relative output current variation is defined as:
LOW level output voltage HIGH level output voltage V
- VDD-0.4
- -
0.4 -
V V
ISET =
IZOUT IZOUT
= 2x
(I |I
2 2
- I 1) + I1 |
;
With I1 @ V1 = 0.6 V, I2 @V2 = VDDCP - 0.7 V (see Figure 3).
CURRENT
IZOUT
I2
I1
VOLTAGE V1 V2
VPH
I2
I1
SR00602
Figure 3. Relative output current variation.
2002 Feb 22
7
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
1.0 FUNCTIONAL DESCRIPTION
Frequency synthesizers, such as Philips Semiconductors' SA8028, are a crucial part of Phase Locked Loops (PLL) for both voice and data devices used in communications. Five components make up the basic PLL (see Figure 4). A very stable, low frequency, signal source (typically a temperature controlled crystal oscillator TCXO_) is used as a reference to the system. A second signal source (typically a VCO) is used to generate the desired output frequency. A phase/frequency detector (PFD) is used to compare the phase/frequency error between the two signals. A loop filter (LPF) rejects undesired noise while also integrating the PFD output current to drive the VCO with the necessary tuning voltage, and a divider in the feedback path is used to down-convert the VCO output frequency to the reference frequency for comparison. The SA8028 is a dual synthesizer that integrates programmable dividers, programmable charge pumps and phase comparators to be implemented as part of RF and IF PLLs. The RF synthesizer operates at VCO input frequencies up to 2.5 GHz, while the IF synthesizer operates at VCO input frequencies up to 760 MHz.
During each RF divider cycle, one divider output pulse is generated. The positive edge of this pulse drives the phase comparator, the negative edge drives the sigma-delta modulator which is of 2nd order and has an effective resolution of 22 bits. Internally, the modulator works with 23 fractional bits K<22:0>, but the LSB (bit K0) is set to `1' internally to avoid limit cycles (cycles of less than maximum length). This leaves 22 bits (K<22:1>) available for external programming. Under these conditions (2nd order modulator, 23 fractional bits, K0 = `1'), all possible sigma-delta sequences are 2*223 divider cycles long, which is the maximum length. The noise shaping characteristic is +20 dB/dec for offset frequencies up to approx. fCOMP/5, which needs to be cancelled by a closed-loop transfer function of sufficient high order. The output of the sigma-delta modulator is 2 bits, which are added to the integer RF division ratio N, such that the momentary division ratios range from (N-1) to (N+2) in steps of 1.
1.2 IF divider
The IFin input drives a pre-amplifier to provide the clock to the first divider stage. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. The allowable divide ratios are from 128 to 16383 (C-word bits <21:8>). Table 14 shows all the possible values that can be programmed into the C-Word for the IF divider.
TCXO PFD
LPF
VCO
INTEGRATOR
1 + N() N DIVIDER
1.3 Reference divider (see Figure 5)
SR02370
Figure 4. PLL block diagram.
1.1 RF Fractional-N divider
The RFin inputs drive a pre-amplifier to provide the clock to the first divider stage. For single ended operation, the signal should be fed (AC-coupled) to one of the inputs while the other one is AC grounded. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The bipolar divider is fully programmable. For allowable division ratios, see the "characteristics" table.
The IF phase detector's reference input is an integer ratio of the reference frequency. The reference divider chain consists of a bipolar input buffer followed by a CMOS divider and a 3-bit binary counter (SA register). The allowable divide ratios, R, are from 4 to 1023 (B-word bits <21:12>) when the 3-bit binary counter (C-word bits <2:0>) is set to all zeros, SA = 000. The 3-bit SA register determines which of the 5 divider outputs (refer to Table 12) is selected as the IF phase detector input (see Figure 5). For the RF synthesizer, the output of the reference input buffer is routed directly (not reference divider) to the input of the RF phase detector.
TO RF PHASE DETECTOR
REFERENCE INPUT
REFERENCE INPUT BUFFER
DIVIDE BY R
/2
/2
/2
/2
SA="100" SA="011" SA="010" SA="001" SA="000" TO IF PHASE DETECTOR
SR02294
Figure 5. Reference divider.
2002 Feb 22
8
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
1.4 Phase detector (see Figure 6)
The reference signal and the RF (IF) divider output are connected to a phase frequency detector that controls the charge pumps. The dead zone (caused by the finite time taken to switch the charge pump current sources on or off) is cancelled by forcing the pumps ON for a minimum time (backlash time, ) at every cycle providing improved linearity.
VDDCP
"1" fREF * see note R
D CLK R
P Q
P-TYPE CHARGE PUMP
"1" IF/RF DIVIDER X D CLK Q N R
IPH
N-TYPE CHARGE PUMP
GNDCP
fREF
R
X
P
N
IPH
SR02413
NOTES: For the RF synthesizer, the output of the reference input buffer is routed directly (not divided) to the input of the RF phase detector. Whereas for the IF synthesizer, the reference input to the IF phase detector is the output from the reference divider. (backlash time) is the delay that fixes the minimum allowable charge pump activity time. Figure 6. Phase detector structure with timing.
2002 Feb 22
9
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
1.5 RF and IF Charge Pumps
The RF phase detector drives the charge pumps on the PHP and PHI pins, while the IF phase detector drives the charge pump on the PHA pin. Both the RF and IF charge pump current values are determined by the current generated at the RSET pin1. The current gain can be further programmed by the CP0, CP1 bits in the C-word, as seen in Table 1.
1.7 Lock Detect
The output LOCK maintains a logic `1' when the IF phase detector (AND/ORed) with the RF phase detector indicates a lock condition. The lock condition for the RF and IF synthesizers is defined as a phase difference of less than "1 period of the frequency at the input REFin+, REFin-. One counter can fulfill the lock condition when the other counter is powered down. Out of lock (logic `0') is indicated when both counters are powered down.
Table 1. RF and IF charge pump currents
CP1 2 0 0 1 1 CP0 0 1 0 1 IPHA 1.5xlSET 0.5xlSET 1.5xlSET 0.5xlSET IPHP 3xISET 1xlSET 3xlSET 1xlSET IPHP-SU 3 15xlSET 5xlSET 15xlSET 5xlSET IPHI 36xlSET 12xlSET 0 0
1.8 Power-down mode
With power applied to the chip, power-down mode can be entered either by hardware (external signal on pin PON) or by software (by programming the PD = Power Down bits () in the B-word). The PON signal is exclusively ORed with the PD bits. If PON = 0, then the part is powered up when PD = 1 (). PON can be used to invert the polarity of the software bits PD. Table 9 of section 2.4.2 illustrates how power-down mode can be implemented. During power-down mode the 3-wire bus remains active and programming-words may be pre-loaded before switching to power-up mode. If the chip is programmed while in power-down mode, the RF divider ratio NRF is internally presented to the RF divider on the next falling edge of STROBE after STROBE has gone high at the end of the A-word. Power-down mode does not reset the sigma-delta modulator., i.e., power-down mode preserves the state of the sigma-delta modulator (as long as power is applied to the chip). To take advantage of the register pre-loading capability while the device is in power-down mode, the B-word needs to be sent a second time (i.e., again, after the A-word), with the PD () bits now programmed for power-up. If power-up mode is to be controlled by hardware, the PON signal must be toggled only after the A-word has been sent and STROBE has gone high and then low. When the synthesizer is reactivated after power-down mode, the IF and reference dividers are synchronized to avoid random phase errors on power-up. There is no power-up synchronization between the RF divider and the reference clock. After power-up, there is a delay of four edges (i.e. 1.5 cycles) of the output clock of the reference divider before the RF phase detector is activated. That means the reference divider must be powered up for the RF phase detector to become active. When initially applying or reapplying power to the chip, and internal power-up reset pulse is generated which sets the programming-words to their default values and also resets the sigma-delta modulator to its "all-0" state. It is also recommended that the D-word be manually reset to all zeros, following initial power-up, to avoid unknown states.
NOTES 1. ISET = VSET/RSET: bias current for charge pumps. 2. CP1 = 1 is used to disable the PHI pump. 3. IPHP-SU is the total current at pin PHP during speed up condition.
1.6 Charge Pumps Speed-up Mode
The RF charge pumps will enter speed-up mode when STROBE goes high after A-word has been sent. They will exit speed-up mode on the next falling edge of STROBE. There is no speed-up mode for the IF charge pump. The charge pump, by default, will automatically go into speed-up mode (which can deliver up to 15*ISET for PHP_SU, and 36*ISET for PHI), based on the strobe pulse width following the A-word to reduce switching speed for large tuning voltage steps (i.e., large frequency steps). Figure 7 shows the recommended passive loop filter configuration. Note: This charge pump architecture eliminates the need for added active switches and reduces external component count. Furthermore, the programmable charge pump gains provide some programmability to the loop filter bandwidth. The duration of speed-up mode is determined by the strobe pulse that follows the A-word. Recommended optimal strobe width is equal to the total loop filter capacitance charge time from VCO control voltage level 1 to VCO control voltage level 2. The strobe width must not exceed this charge time. An external data processing unit controls the width of the strobe pulse (e.g., x number of clock cycles). In addition, charge pumps will stay in speed-up mode continuously while Tspu = 1 (in D-word ). The speed-up mode can also be disabled by programming Tdis-spu = 1 (in D-word ).
R2 PHP[PHP-SU] R1 PHI C1 C2 C3
VCO
SR02356
Figure 7. Typical passive 3-pole loop filter.
2002 Feb 22
10
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
2.0 SERIAL PROGRAMMING BUS
A simple 3-line bidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLOCK and STROBE. When the STROBE = 0, the clock driver is enabled and on the positive edges of the CLOCK signal, DATA is clocked into temporary shift registers. When the STROBE = 1, the clock is disabled and the data in the shift register is latched into different working registers, depending on the address bits. In order to fully program the circuit, 3 words must be sent in the following order: C, B, and A. An additional word, the D-word, is for test purposes only: all bits in this test word should be initialized to 0 for normal operation. The N value of the B-word is stored temporarily until the A-word is loaded to avoid temporarily false N settings, while the corresponding fractional ratio Kn is not yet active. When a new fractional ratio is loaded through the A-word, the fractional sigma delta modulator is not reset, i.e., it will start the new fractional sequence from the last state of the previously executed sequence. A typical programming sequence is illustrated in Figure 10.
When loading several words in series, the minimum STROBE high time between words must be observed (refer to Figure 8). Unlike the earlier SA80xx family members, SA8028 has the built-in feature to output the contents of an addressable internal register. For the current SA8028, only the momentary division ratio N (RF divider) can be retrieved through the serial bus. The handshake protocol requires a "request to read" to be sent prior to each "read", i.e., by sending a D-word with the TreadN-bit () set to "high". Immediately after the transition of "STROBE" from low-to-high, four (4) clock pulses are needed to prepare the data for output and another nine (9) clock pulses are needed to accomplish the serial reading with LSB first. A high-to-low transition of "STROBE" then resets the serial bus to the input mode. The timing diagram is presented in Figure 9. In general, a high-to-low transition of the "STROBE" signal will instantaneously reset the serial bus to the input mode, even when the chip is in the output mode.
Table 2. Serial bus timing requirements (see Figures 8 and 9)
VDD = VDDCP =+3.0 V; Tamb = +25 C unless otherwise specified. (Guaranteed by design.) SYMBOL tr tf Tcy tSTART, tSTART;R tW tSU;E tRESET tSU;DAT tHD;DAT tSU;DAT;R PARAMETER Input rise time Input fall time Clock period Delay to rising clock edge Minimum inactive pulse width Enable set-up time to next clock edge Reset data line to input mode Input data to clock set-up time Input data to clock hold time Input clock to data set-up time MIN. - - 100 40 1/fCOMP 20 20 20 20 20 TYP. 10 10 - - - - - - - - MAX. 40 40 - - - - - - - - UNIT ns ns ns ns ns ns ns ns ns ns Serial programming clock; CLK
Enable programming; STROBE
Register serial input data; DATA (I)
Register serial output data; DATA (O)
tSU;DAT
tf
tr
TCY
tHD;DAT
tSU;E
CLK
DATA
LSB
MSB
ADDRESS
>=0
STROBE tSTART
tW
SR02296
Figure 8. Serial bus "Write" timing diagram.
2002 Feb 22
11
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
tr
Tcy
tf
tSU:DAT;R
tRESET
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
DATA
LSB
MSB
DEVICE I/O:
I
I
O
O
O
O
O
O
O
O
O
I
STROBE
tSTART;R
SR02372
Figure 9. Serial bus "Read" timing diagram.
2002 Feb 22
12
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
POWER-ON
PROGRAM D WORD - SET DEFAULT
PROGRAM C WORD - SELECT SA - SET CHARGE PUMP GAIN - SET IF DIVIDER - SELECT LOCK DETECT
PROGRAM B WORD - SET RF DIVIDER N - SET POWER-UP OPTION - SET REF DIVIDER - SET RESET-BITS
PROGRAM A WORD - SET FRACTIONAL VALUE K
READY TO OPERATE
PROGRAM A WORD
Y
CHANGE FRACTIONAL VALUE K N
CHANGE RF DIVIDER N
Y
N
PROGRAM C WORD
Y
CHANGE IF FREQUENCY N
PROGRAM B WORD
Y
POWER DOWN N
PROGRAM B WORD
Y
POWER UP
N POWER OFF
SR02380
Figure 10. Typical programming sequence
2002 Feb 22
13
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
2.1 Data format
Each of the 4 word registers contains 24 programmable bits. Data is serially clocked in on the rising edge of each clock pulse with the LSB first in, and MSB last in.
Table 3. Format of programmed data
LAST IN MSB p23 p22 p21 p20 SERIAL PROGRAMMING FORMAT .. / .. .. / .. p1 FIRST IN LSB p0
2.2 Register addressing Table 4. Register addressing
Bit A-word address B-word address C-word address D-word address <23> 0 0 1 1 <22> 0 1 0 1 <21> x x x 0
Notice that the register addresses are the MSB in each word; thus, the last to be clocked into the registers.
2.3 A-word register Table 5. A-word, length 24 bits
Last IN <21> <20> <19> <18> <17> <16> <15> <14> <13> <12> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0>
Address
0 0
Fractional ratio Kn
K22 K21 K20 K19 K18 K17 K16 K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1
Default :
0
0
0
0
1
1
0
1
0
1
1
0
1
1
1
0
1
0
0
1
1
1
A word address Fractional ratio select
Fixed to 00. Kn sets the fractional part of the total division ratio. To avoid limit cycles the K0 bit is internally set to "1"
2.3.1 The fractional multiplier
The A-word register is dedicated for programming the RF loop, fractional multiplier (the sigma-delta modulator) which has an effective resolution of 22 bits. The modulator works with 23 bits, Kn<22:0>. However, this K0 bit is set to `1' internally to avoid limit cycles (cycles of less than maximum length). This leaves 22 bits (Kn<22:1>) available for external programming. Refer to Table 6. Calculating the desired VCO output frequency can be easily accomplished by using the following equation, Equation (1). f VCO + f ref N ) 2 Kn <22:1> ) 1 2 23 (1)
where fref is the reference frequency at the REF input pin and N is the integer multiplier. Kn, once again, is the fractional multiplier. Example: Determine the Kn value required for generating a VCO frequency of 2100 MHz with a reference frequency of 19.68 MHz.
f VCO f ref
-N 2
2 23
Kn<22:1> +
Kn<22:1> +
2100 MHz -106 19.68 MHz
2 23
2
+ 2966702
2002 Feb 22
14
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
Table 6. Kn values for the fractional divider
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Kn
0 0 0 0 - 1 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 1 - 1 1
0 0 0 0 - 1 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 1 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 1 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 1 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 1 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 1 - 1 1
0 0 0 0 - 0 - 1 1
0 0 0 0 - 1 - 1 1
0 0 0 1 - 1 - 1 1
0 1 1 0 - 1 - 1 1
1 0 1 0 - 0 - 0 1
1 2 3 4 ... 2966702 ... 4194302 4194303
2.4 B-word register Table 7. B-word, length 24 bits
Last IN <21> <20> <19> <18> <17> <16> <15> <14> <13> <12> <11> Reset bit R2 R1 R0 PDref <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0>
Address
0 1 R9 R8 R7
Reference divider ratio Rn
R6 R5 R4 R3
Power Down IF RF N8 N7
RF Divider integer ratio N
N6 N5 N4 N3 N2 N1 N0
Default: R-Divider Reset bit Power-down N-Divider
0
0
0
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
0
0
B-word address
Fixed to 01 R0..R9, Reference divider values, see section "characteristics" for allowed divider ratios. 1 Pdref : powers down (=resets) the reference divider See Truth Table 9 Nn sets the integer part of the RF divider ratio, see section "characteristics" for allowed ratios.
2.4.1 The RF divider
Programming the RF divider to obtain the desired VCO output frequency is done by programming the B-word followed by the A-word. The integer divider bits N<8:0> are in the B-word, whereas the fractional divider bits Kn<22:1> are in the A-word. Allowable integer division ratios are shown in Table 8. The N value, from Equation (2), is simply the whole number of times the reference frequency goes into the desired VCO output frequency. Recall that the reference frequency for the RF loop is not reduced prior to the phase detector. In other words, the frequency at the input of the REFin is the comparison frequency. MODULO N+ f VCO * f ref f ref
900 MHz f VCO f ref
(2)
MODULO 19.68 MHz N + 900 MHz * 19.68 MHz 19.68 MHz N + 45.7317073170...- 14.4 + 45 19.68
2002 Feb 22
15
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
Table 8. Allowable integer values (N) for the RF divider
0 -- -- -- -- 1 0 -- -- -- -- 1 0 -- -- -- -- 1 1 -- -- -- -- 1 0 -- -- -- -- 1 0 -- -- -- -- 1 0 -- -- -- -- 1 0 -- -- -- -- 0 1 -- -- -- -- 1 N 33 ... ... ... ... 509
2.4.2 Power-down
If the chip is programmed while in power-up mode, the loading of the A-word and of the N values in the B-word are synchronized to the RF divider output pulse. The data takes effect internally on the second falling edge of the RF divider output pulse after STROBE has gone high at the end of the A-word. STROBE does not need to be held high until that second falling edge of the RF divider output pulse has occurred. If the chip is programmed while in power-down mode, this synchronization scheme is disabled. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programmed data, even during power-down. To take advantage of the program register pre-loading capability while the device is in power-down mode, the B-word needs to be sent a second time (i.e. again, after the A-word), with the PD bits now programmed for power-up. If power-up mode is to be controlled by hardware, the PON signal must be toggled only after the A-word has been sent and STROBE has gone high and then low. When the synthesizer is reactivated after power-down mode, the IF and reference dividers are synchronized to avoid random phase errors on power-up. There is no power-up synchronization between the RF divider and the reference clock. However, after power-up, there is a delay of four edges (i.e. 1.5 cycles) of the output clock of the reference divider before the RF phase detector is activated. That means the reference divider must be powered up for the RF phase detector to become active. When initially applying or re-applying power to the chip, an internal power-up reset pulse is generated which sets the programming-words to their default values and also resets the sigma-delta modulator to its "all-0" state. It is also recommended that the D-word be manually reset to all zeros, following initial power-up, to avoid unknown states.
Table 9. Power-down Truth Table
PON 0 0 0 0 1 1 1 1 IF 0 0 1 1 0 0 1 1 RF 0 1 0 1 0 1 0 1 IF OFF OFF ON ON ON ON OFF OFF RF OFF ON OFF ON ON OFF ON OFF
2002 Feb 22
16
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
2.4.3 Programming the IF Reference Divider
The IF phase detector's reference input is an integer multiple of the frequency at the input of the REFin pin. The reference divider has 10 programmable bits, for allowable divide ratios, R, from 4 to 1023 when the 3 bit binary SA counter (refer to section 2.5.1) is set to all zeros. Table 10 lists the allowable R values.
Table 10. R Values for the IF Reference Divider
0 0 0 -- 1 1 0 0 0 -- 1 1 0 0 0 -- 1 1 0 0 0 -- 1 1 0 0 0 -- 1 1 0 0 0 -- 1 1 0 0 0 -- 1 1 1 1 1 -- 1 1 0 0 1 -- 1 1 0 1 0 -- 0 1 R 4 5 6 ... 1022 1023
2.5 C-word Register Table 11. C-word, length 24 bits
Last IN Address 1 0 A13 A12 A11 A10 A9
<21> <20> <19> <18> <17> <16> <15> <14> <13> <12> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0>
IF Divider An
A8 A7 A6 A5 A4 A3 A2 A1 A0
CP
CP1 CP0
Lock detect
L1 L0
Reset bit
Tsigrst SA2
SA
SA1 SA0
Default:
0
0
0
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
0
C-word address A-Divider Charge pump current Ratio Lock detect Reset bit
Fixed to 10 A0..A13, IF divider values , see section "characteristics for allowed for divider ratios. CP1, CP0: Charge pump current ratio, see table of charge pump currents. See Table 13. 1 Tsigrst : resets the sigma-delta modulator after each loading of an A-word. ( It is held in the reset state between the first and second falling edge of the RF divider output pulse after STROBE has gone high at the end of the A-word. ) SA Comparison divider select for IF phase detector
IF comparison select
2.5.1 Programming the SA Counter
The 3 bit SA register determines which of the 5 divider outputs (refer to table 11) is selected as the IF phase detector's input (see Figure 5).
Table 12. IF phase comparator frequency
0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Divide Ratio R R*2 R*4 R*8 R * 16 IF Phase Comparator Frequency fref 1 / R fref / (R * 2) fref / (R * 4) fref / (R * 8) fref / (R * 16)
NOTES: 1. fref is the input frequency at the REFin pin.
2.5.2 Programming the Reset Bits ,
The reset bits offer extra flexibility. The default value for bits , are all zeros. Bit disables the IF reference divider and allows for extra savings of approximately 200 A when set to `1'. However, this bit must initially be set to `0' during any power-up sequence. The RF phase detector is activated after a delay of four edges of the reference divider output clock. Bit resets the sigma-delta modulator after each loading of an A-word. It is held in the reset state between the first and second falling edge of the RF divider output pulse after STROBE has gone high at the end of the A-word.
2002 Feb 22
17
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
2.5.3 Programming the Lock Detect
Lock detection is available only for the RF and IF phase detector. A `0' in bit is used for TTL, while a `1' in bit is used for RTL.
Table 13. Lock detect select
L1 0 0 1 1 L0 0 1 0 1 Select RF/IF (push/pull)1 RF/IF (open drain) RF (push/pull) IF (push/pull)
NOTE: 1. Combined RF_IF lock detect signal present at the lock pin (push/pull).
2.5.4 Programming the Charge Pump Gain
The RF phase detector drives the charge pumps on the PHP and PHI pins, while the IF phase detector drives the charge pump on the PHA pin. The current generated at the RSET pin determines both the RF and IF charge pump current values in conjunction with the current gain programmed by the CP0, CP1 bits in the C-word, as seen in Table 1. For more information on charge pump speed-up mode, refer to section 1.6.
2.5.5 Programming the IF Divider for the IF Loop
The divider is a fully programmable counter. The allowable divide ratios, A, are from 128 to 16383, bits . Table 14 shows all the possible values that can be programmed into the C-word for the IF divider.
Table 14. Allowable Values (A) for the IF Divider
C21 0 0 0 -- 1 1 C20 0 0 0 -- 1 1 C19 0 0 0 -- 1 1 C18 0 0 0 -- 1 1 C17 0 0 0 -- 1 1 C16 0 0 0 -- 1 1 C15 1 1 1 -- 1 1 C14 0 0 0 -- 1 1 C13 0 0 0 -- 1 1 C12 0 0 0 -- 1 1 C11 0 0 0 -- 1 1 C10 0 0 0 -- 1 1 C9 0 0 1 -- 1 1 C8 0 1 0 -- 0 1 A 128 129 130 ... 16382 16383
2.6 D-word Register
The D-word is for test purposes only. All bits in this test word should be initialized to 0 for normal operation. When initially applying or re-applying power to the chip, an internal power-up reset pulse if generated which sets the programming-words to their default values and which resets the sigma-delta modulator to its "all-0" state. It is also recommended that the D-word be manually reset to all zeros, following initial power-up, to avoid unknown states.
Table 15. D-word, length 24 bits
Last IN
<21> <20> <19> <18> <17> <16> <15> <14> <13> <12> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0>
Address
1 1 0 - - - - Tdis-spu Tspu - - -
Synthesizer Test bits
TreadN - - - - - - - - - - -
Default D word address Tdis-spu Tspu: Speed up TreadN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Fixed to 110. Speed-up mode disabled. Speed-up mode always on. NOTE: All other test bits must be set to 0 for normal operation. NOTE: All other test bits must be set to 0 for normal operation.
Used to "request to read" bit settings from bits . For more information on reading out the N value, refer to Section 2.0, Serial Programming Bus.
2002 Feb 22
18
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
3.0 Typical Performance Characteristics
3000 Iset = 204 A 2000 Iset = 163 A 1000 1000 Iset = 81 A Icp (A) 0 Iset = 81 A -1000 Iset = 163 A -2000 -2000 Iset = 204 A -3000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 -2500 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 2.75 500 Icp 0 (A) -500 -1000 -1500 -40C +25C +85C 2500 2000 1500
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR02414
SR02389
Figure 11. PHI_SU charge pump output vs. Iset (CP = 01_12x, VDD = 3.0 V, Temp = 25 C)
Figure 12. PHI_SU charge pump output vs. temperature (CP = 01_12x, VDD = 3.0 V, Iset = 163 A)
8000
8000 Iset = 204 A 6000 Iset = 163 A 4000 2000 Icp (A) 0 -2000 -4000 -6000 -8000 Iset = 81 A Iset = 81 A
6000
4000 -40C +25C +85C
2000 Icp (A) 0
-2000 Iset = 163 A Iset = 204 A 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75
-4000
-6000 -8000
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
COMPLIANCE VOLTAGE (V)
SR02390
COMPLIANCE VOLTAGE (V)
SR02391
Figure 13. PHI_SU charge pump output vs. Iset (CP = 00_36x, VDD = 3.0 V, Temp = 25 C)
Figure 14. PHI_SU charge pump output vs. temperature (CP = 00_36x, VDD = 3.0 V, Iset = 163 A)
2002 Feb 22
19
2.50
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
800 Iset = 204 A 600
600
400 400 200 Icp (A) 0 Iset = 81 A -200 -400 -600 Iset = 204 A -800 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 -600 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 -40C +25C +85C 2.50 2.75 2.75 Iset = 163 A -200 Iset = 163 A Iset = 81 A 200 -40C Icp (A) 0 +25C +85C
-400
COMPLIANCE VOLTAGE (V)
SR02393
COMPLIANCE VOLTAGE (V)
SR02392
Figure 15. PHP charge pump output vs. Iset (CP = 10_3x, VDD = 3.0 V, Temp = 25 C)
250 Iset = 204 A 200 150 100 50 Icp (A) 0 -50 -100 -150 -200 Iset = 204 A -250 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 Iset = 163 A Iset = 81 A Iset = 81 A 200
Figure 16. PHP charge pump output vs. temperature (CP = 10_3x, VDD = 3.0 V, Iset = 163 A)
150 Iset = 163 A 100 50 Icp (A) 0 -50 -100 -150 -200 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25
COMPLIANCE VOLTAGE (V)
SR02394
COMPLIANCE VOLTAGE (V)
SR02395
Figure 17. PHP charge pump output vs. Iset (CP = 11_1x, VDD = 3.0 V, Temp = 25 C)
Figure 18. PHP charge pump output vs. temperature (CP = 11_1x, VDD = 3.0 V, Iset = 163 A)
2002 Feb 22
20
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
1200 1000 800 600 400 200 Icp (A) 0 -200 -400 -600 -800 Iset = 163 A Iset = 81 A Iset = 81 A Iset = 204 A Iset = 163 A
1000 800 600 400 200 Icp (A) 0 -200 -400 -600 -800 -40C +25C +85C
-1000 Iset = 204 A -1200 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 -1000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 2.75
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR02396
SR02397
Figure 19. PHP_SU charge pump output vs. Iset (CP = 01_5x, VDD = 3.0 V, Temp = 25 C)
4000 Iset = 204 A 3000
Figure 20. PHP_SU charge pump output vs. temperature (CP = 01_5x, VDD = 3.0 V, Iset = 163 A)
3000
2000 2000 Iset = 163 A 1000 1000 Icp (A) 0 -1000 Iset = 81 A -1000 -2000 -3000 Iset = 163 A Iset = 204 A Iset = 81 A Icp (A) 0 -40C +25C +85C
-2000
-4000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 -3000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
COMPLIANCE VOLTAGE (V)
SR02398
COMPLIANCE VOLTAGE (V)
SR02399
Figure 21. PHP_SU charge pump output vs. Iset (CP = 00_15x, VDD = 3.0 V, Temp = 25 C)
Figure 22. PHP_SU charge pump output vs. temperature (CP = 00_15x, VDD = 3.0 V, Iset = 163 A)
2002 Feb 22
21
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
150 Iset = 204 A 100
100 80 60 Iset = 163 A 40 -40C Iset = 81 A 20 Icp (A) 0 Iset = 81 A -20 -40 -60 +25C +85C
50
Icp 0 (A)
-50 Iset = 163 A -100 Iset = 204 A -150 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25
-80 -100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.00 3.25 3.25
COMPLIANCE VOLTAGE (V)
SR02400
COMPLIANCE VOLTAGE (V)
SR02401
Figure 23. PHA charge pump output vs. Iset (CP = 11_0.5x, VDD = 3.0 V, Temp = 25 C)
400 Iset = 204 A 300
Figure 24. PHA charge pump output vs. temperature (CP = 11_0.5x, VDD = 3.0 V, Iset = 163 A)
300
200 200 100 Iset = 81 A Icp 0 (A) -100 -200 -300 Iset = 204 A -400 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 -300 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 Iset = 81 A -100 Iset = 163 A -200 Icp (A) 0 Iset = 163 A 100 -40C +25C +85C
COMPLIANCE VOLTAGE (V) COMPLIANCE VOLTAGE (V)
SR02402
SR02403
Figure 25. PHA charge pump output vs. Iset (CP = 10_1.5x, VDD = 3.0 V, Temp = 25 C)
Figure 26. PHA charge pump output vs. temperature (CP = 10_1.5x, VDD = 3.0 V, Iset = 163 A)
2002 Feb 22
22
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
INPUT FREQUENCY (MHz)
SR02404
Figure 27. RF (main) divider input sensitivity vs. frequency and supply voltage (Temp = 25 C, Iset = 164 A, N = 509)
Figure 28. RF (main) divider input sensitivity vs. frequency and temperature (VCC = 3.0 V, Iset = 164 A, N = 509)
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
INPUT FREQUENCY (MHz)
SR02406
Figure 29. RF (main) fractional divider input sensitivity vs. frequency and supply voltage (Temp = 25 C, Iset = 164 A, N = 509.5)
Figure 30. RF (main) fractional divider input sensitivity vs. frequency and temperature (VCC = 3.0 V, Iset = 164 A, N = 509.5)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45
MINIMUM INPUT LEVEL (dBm)
MINIMUM INPUT LEVEL (dBm)
2.7V 3.0V 3.6V
20 60 100 140 180 220 260 300 340 380 420 460 500 540 580 620 660 700 740 780 820 860 900 940 980 1020
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45
INPUT FREQUENCY (MHz)
SR02408
Figure 31. IF (aux) divider input sensitivity vs. frequency and supply voltage (Temp = 25 C, Iset = 164 A, divider ratio = 16383)
Figure 32. IF (aux) divider input sensitivity vs. frequency and temperature (VCC = 3.0 V, Iset = 164 A, divider ratio = 16383)
2002 Feb 22
23
20 60 100 140 180 220 260 300 340 380 420 460 500 540 580 620 660 700 740 780 820 860 900 940 980 1020
INPUT FREQUENCY (MHz)
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
INPUT FREQUENCY (MHz)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48
MINIMUM INPUT LEVEL (dBm)
3.6V
MINIMUM INPUT LEVEL (dBm)
2.7V 3.0V
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
INPUT FREQUENCY (MHz)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48
MINIMUM INPUT LEVEL (dBm)
MINIMUM INPUT LEVEL (dBm)
2.7V 3.0V 3.6V
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48
-40C 25C 85C
SR02405
-40C 25C 85C
SR02407
-40C 25C 85C
SR02409
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68
INPUT FREQUENCY (MHz)
SR02410
Figure 33. Reference divider input sensitivity vs. frequency and supply voltage (Temp = 25 C, Iset = 164 A, divider ratio = 1023)
Figure 34. Reference divider input sensitivity vs. frequency and temperature (VCC = 3.0 V, Iset = 164 A, divider ratio = 1023)
9.00
8.50
TOTAL CURRENT (mA)
8.00
7.50
7.00
-40C 25C 85C
6.50
6.00 2.6
2.8
3
3.2
3.4
3.6
3.8
SUPPLY VOLTAGE (V)
SR02412
Figure 35. Total supply current vs. temperature (Iset = 163 A Fcomp = 20 MHz)
2002 Feb 22
24
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68
INPUT FREQUENCY (MHz)
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40
2.7V
MINIMUM INPUT LEVEL (dBm)
3.0V 3.6V
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40
-40C 25C 85C
MINIMUM INPUT LEVEL (dBm)
SR02411
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
4.0 Application Schematic
SA8028W
2002 Feb 22
25
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
HBCC24: plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm
SOT564-1
2002 Feb 22
26
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
NOTES
2002 Feb 22
27
Philips Semiconductors
Product data
2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers
SA8028
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 02-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 09499
Philips Semiconductors
2002 Feb 22 28

▲Up To Search▲

Price & Availability of SA8028

	To Download SA8028 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .